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NBSG111 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs
*Reduced Swing ECL
Description http://onsemi.com MARKING DIAGRAM*
The NBSG111 is a 1-to-10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single-ended NECL or PECL inputs and the VMM pin is used for LVCMOS inputs. For single-ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open.
Features
SG 111 LYW FCBGA-49 BA SUFFIX CASE 489A SG111 L Y W = Device Code = Wafer Lot = Year = Work Week
*For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
* * * * * * * * * *
Maximum Input Clock Frequency > 6 GHz Typical Maximum Input Data Rate > 6 Gb/s Typical 300 ps Typical Propagation Delay 60 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices VBB and VMM Reference Voltage Output
(c) Semiconductor Components Industries, LLC, 2007
January, 2007 - Rev. 8
1
Publication Order Number: NBSG111/D
NBSG111
1 2 3 4 5 6 7
A
VEE
Q9
Q9
Q8
Q8
Q7
VEE
B
Q0
VMM
CLK1
CLK1
VCC
NC
Q7
C
Q0
VEE
VTCLK1
VTCLK1
VTSEL
SEL
Q6
D
Q1
EN
VTEN
VCC
VTSEL
SEL
Q6
E
Q1
EN
VTEN
VTCLK0
VTCLK0
VEE
Q5
F
Q2
NC
VCC
CLK0
CLK0
VBB
Q5
G
VEE
Q2
Q3
Q3
Q4
Q4
VEE
Figure 1. BGA-49 Pinout (Top View)
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Table 1. PIN DESCRIPTION
Pin A1,A7,G1,G7,C2,E6 F3,D4,B5 B2 F6 E4 F4 E5 F5 C4 B4 C3 B3 B1,D1,F1,G3,G5,F7, D7,B7,A5,A3 C1,E1,G2,G4,G6,E7, C7,A6,A4,A2 D5 D6 C5 C6 D3 D2 E3 E2 F2,B6 Name VEE VCC VMM VBB VTCLK0 CLK0 VTCLK0 CLK0 VTCLK1 CLK1 VTCLK1 CLK1 Q[0:9] Q[0:9] VTSEL SEL VTSEL SEL VTEN EN VTEN EN NC I/O - - - - - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input - ECL, CML, LVCMOS, LVDS, LVTTL Input - Description Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. LVCMOS Reference Voltage Output (VCC - VEE) / 2. ECL Reference Voltage Output Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Noninverted Differential Input CLK0. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Inverted Differential Input CLK0. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin 1. See Table 4. (Note 1) Noninverted Differential Input CLK1. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK1. See Table 4. (Note 1) Inverted Differential Input CLK1. Internal 75 kW to VEE and 36.5 kW to VCC. Noninverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC - 1.5 V Inverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC - 1.5 V Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Noninverted Differential Select Logic Input. Internal 75 kW to VEE. Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Inverted Differential Select Logic Input. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin for EN. See Table 4. (Note 1) Noninverted Differential Output Enable Pin. Internal 75 kW to VEE. Internal 50 W termination Pin for EN. See Table 4. (Note 1) Inverted Differential Output Enable Pin. Internal 75 kW to VEE and 36.5 kW to VCC. No Connect. The NC Pins are Electrically Connected to the Die and "MUST BE" Left Open.
1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self-oscillation.
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Table 2. FUNCTION TABLE
SEL L L H H EN L H L H Active Input Disabled Outputs CLK0, CLK0 Disabled Outputs CLK1, CLK1
2. SEL/EN are the inverse of SEL/EN unless specified otherwise. Q0 (B1) Q0 (C1) Q1 (D1) Q1 (E1) (C5) VTSEL (C6) SEL RTIN R2 R1 Q2 (F1) Q2 (G2) Q3 (G3) (E4) VTCLK0 (F4) CLK0 (F5) CLK0 (E5) VTCLK0 (B4) CLK1 (C4) VTCLK1 (B3) CLK1 (C3) VTCLK1 (D6) SEL (D5) VTSEL RTIN R2 RTIN RTIN R2 RTIN R1 R2 1 (E2) EN (E3) VTEN 0 (D3) VTEN (D2) EN R2 SYNC R1 RTIN R2 (F6) VBB (A1, A7, G1, G7) VEE RTIN Q3 (G4) Q4 (G5) Q4 (G6) Q5 (F7) Q5 (E7) Q6 (D7) Q6 (C7) Q7 (B7) Q7 (A6) Q8 (A5) Q8 (A4) (B5, D4, F3) VCC (B2) VMM Q9 (A3) Q9 (A2)
R1 R2
RTIN R2
Figure 2. Logic Diagram
Table 3. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED CONNECTIONS Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL to VCC Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Together Bias VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques See Text on Page 1. Unused Differential Input Switching Voltage Reference Range is from VEE + 1125 mV to VCC - 75 mV
RSECL, PECL, NECL LVTTL, LVCMOS
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Table 4. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor, R2 (CLK0, CLK0, CLK1, CLK1, SEL, SEL, EN, EN) Internal Input Pullup Resistor, R1 (CLK0, CLK1, SEL, EN) ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 36.5 kW > 2 kV > 100 V > 1 kV Level 3 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 479
Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol VCC VI VEE VINPP IOUT IIN IBB IMM TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Negative Input Negative Power Supply Differential Input Voltage |CLK - CLK| Output Current Input Current Through RT (50 W Resistor) VBB Sink/Source VMM Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM 2S2P (Note 4) < 15 sec. 49 FCBGA 49 FCBGA 49 FCBGA Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V VCC = 0 V VCC - VEE w 2.8 V VCC - VEE t 2.8 V Continuous Surge Static Surge VI VCC VI VEE Condition 2 Rating 3.6 3.6 -3.6 -3.6 2.8 |VCC - VEE| 25 50 45 80 1 1 -40 to +70 -65 to +150 67 57 2 to 4 225 Units V V V V V V mA mA mA mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power).
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Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR VMM RTIN IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 6) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Notes 8 and 9) Input LOW Voltage (Single-Ended) (Notes 8 and 10) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) LVCMOS Output Voltage Reference (@ 2.5 VCC) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 70 1365 305 VTHR + 75 VIH - 2500 1025 1.2 Typ 85 1520 420 VCC - 1000* VCC - 1400* 1100 Max 110 1615 545 VCC VTHR - 75 1265 2.5 Min 70 1410 305 VTHR + 75 VIH - 2500 1025 1.2 25C Typ 85 1530 420 VCC - 1000* VCC - 1400* 1100 Max 110 1660 545 VCC VTHR - 75 1265 2.5 Min 70 1435 305 VTHR + 75 VIH - 2500 1025 1.2 70C Typ 85 1560 420 VCC - 1000* VCC - 1400* 1100 Max 110 1685 545 VCC VTHR - 75 1265 2.5 Unit mA mV mV mV mV mV V mV W mA mA
1050 45
1250 50 30 25
1450 55 100 100
1050 45
1250 50 30 25
1450 55 100 100
1050 45
1250 50 30 25
1450 55 100 100
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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Table 7. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR VMM RTIN IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 6) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Notes 8 and 9) Input LOW Voltage (Single-Ended) (Notes 8 and 10) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) LVCMOS Output Voltage Reference (@ 3.3 VCC) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 70 2165 305 VTHR + 75 VIH - 2500 1825 1.2 Typ 85 2320 420 VCC - 1000* VCC - 1400* 1900 Max 110 2415 545 VCC VTHR - 75 2065 3.3 Min 70 2210 305 VTHR + 75 VIH - 2500 1825 1.2 25C Typ 85 2330 420 VCC - 1000* VCC - 1400* 1900 Max 110 2460 545 VCC VTHR - 75 2065 3.3 Min 70 2235 305 VTHR + 75 VIH - 2500 1825 1.2 70C Typ 85 2360 420 VCC - 1000* VCC - 1400* 1900 Max 110 2485 545 VCC VTHR - 75 2065 3.3 Unit mA mV mV mV mV mV V mV W mA mA
1450 45
1650 50 30 25
1850 55 100 100
1450 45
1650 50 30 25
1850 55 100 100
1450 45
1650 50 30 25
1850 55 100 100
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. VMM varies (VCC - VEE) / 2 with VCC and VEE. 6. All outputs loaded with 50 W to VCC - 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 8. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 9. VIH cannot exceed VCC. 10. VIL always w VEE. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. VMM varies (VCC - VEE) / 2 with VCC and VEE. *Typicals used for testing purposes.
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Table 8. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 12) -40C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 13) Output Voltage Amplitude Input HIGH Voltage (Single-Ended) (Notes 15 and 16) Input LOW Voltage (Single-Ended) (Notes 15 and 17) NECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) LVCMOS Output Voltage Reference (@ - 2.5 VEE) (@ - 3.3 VEE) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 70 -1135 305 VTHR + 75 VIH - 2500 -1475 Typ 85 -980 420 VCC - 1000* VCC - 1400* -1400 Max 110 -885 545 VCC VTHR - 75 -1235 0.0 Min 70 -1090 305 VTHR + 75 VIH - 2500 -1475 25C Typ 85 -970 420 VCC - 1000* VCC - 1400* -1400 Max 110 -840 545 VCC VTHR - 75 -1235 0.0 Min 70 -1065 305 VTHR + 75 VIH - 2500 -1475 70C Typ 85 -940 420 VCC - 1000* VCC - 1400* -1400 Max 110 -815 545 VCC VTHR - 75 -1235 0.0 Unit mA mV mV mV mV mV V
VEE+1.2
VEE+1.2
VEE+1.2
VMM
-1450 -1850 45
-1250 -1650 50 30 25
-1050 -1450 55 100 100
-1450 -1850 45
-1250 -1650 50 30 25
-1050 -1450 55 100 100
-1450 -1850 45
-1250 -1650 50 30 25
-1050 -1450 55 100 100
mV
RTIN IIH IIL
W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. 13. All outputs loaded with 50 W to VCC - 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 16. VIH cannot exceed VCC. 17. VIL always w VEE. *Typicals used for testing purposes.
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Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
-40C Symbol VOUTPP tPLH, tPHL tSKEW Characteristic Output Voltage Amplitude (See Figure 3) (Note 18) fin < 3 GHz fin = 5.5 GHz Min 305 180 250 430 400 Typ 420 250 300 550 450 2 5 15 110 110 70 70 0.5 2.0 350 700 500 15 20 85 110 110 Max Min 305 150 250 430 400 25C Typ 420 220 300 550 450 2 5 15 70 70 0.5 14 75 2600 75 2600 75 2600 mV ps 2.0 350 700 500 15 20 85 115 115 Max Min 305 100 250 430 400 70C Typ 420 200 300 600 480 2 5 15 80 80 0.5 2.0 350 750 550 15 20 85 Max Unit mV ps
Propagation Delay to Output Differential Output Enable Clock Select Duty Cycle Skew (Note 19) Within-Device Skew (Note 20) Device-to-Device Skew (Note 21) Setup Time to CLK (EN to Selected CLK0:1) Hold Time (EN to Selected CLK0:1) RMS Random Clock Jitter(Figure 3) (Note 23) fin = 5 GHz Peak-to-Peak Data Dependent Jitter (Note 24) fin = 5 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 22) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q
ps
tS tH tJITTER
ps ps ps
VINPP tr tf
40
60
80
40
60
80
40
60
80
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 18. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC - 1.5 V. Input edge rates 40 ps (20% - 80%). 19. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform (Figure 4). 20. Within-Device skew is measured between outputs under identical transitions and conditions on any one device. 21. Device-to-Device skew for identical transitions at identical VCC levels. 22. VINPP (MAX) cannot exceed VCC - VEE (applicable only when VCC -VEE t 2600 mV). 23. Additive RMS jitter with 50% duty cycle clock signal at 5 GHz. 24. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at 5 Gb/s.
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550 OUTPUT VOLTAGE AMPLITUDE (mV) 10.0 9.0 RMS JITTER (ps) 450 Q AMP (mV) 3.3 V 350 2.5 V 250 RMS JITTER (ps) 150 1 2 3 4 5 6 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 4. AC Reference Measurement
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NBSG111BA NBSG111BAR2 Package FCBGA-49 FCBGA-49 Shipping 100 Units / Tray 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
FCBGA-49 BA SUFFIX PLASTIC 8x8 mm (1.0 mm pitch) BGA FLIP CHIP PACKAGE CASE 489A-02 ISSUE A
A B D
TERMINAL A1 CORNER
A A2 Z
E
NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE C. 4. DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 6. 489A-01 OBSOLETE, NEW STANDARD 489A-02. DIM A A1 A2 b D D1 E E1 e MILLIMETERS MIN MAX --- 1.40 0.3 0.5 0.91 REF 0.40 0.60 8.00 BSC 6.00 BSC 8.00 BSC 6.00 BSC 1.00 BSC
4X
0.15 C D1 e
A FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA
e E1
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
DETAIL A
B C D E F G 7 6 5 4 3 2 1 49 X
Z
NOTE 5
b NOTE 3 0.15 0.08
M M
0.20 C CA B C
NOTE 4 SEATING PLANE
C
0.12 C
49 X
A1
VIEW Z-Z
DETAIL A (ROTATED 90 _ C.W.)
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NBSG111/D

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